Remote Side-Channel Disassembly on FPGAs
Summary
For my dissertation I am creating and evaluating a system for remote side-channel disassembly. I am using ring ocialltor power monitors implemented in FPGA fabric to monitor the side-channel leakage from a general purpose processor (GPP) that is on the same chip die.
Motivation
As we adopt new technologies, we must always be cautious of the potential vulnerabilities that they may introduce. One technology that has a lot of potential are hybrid FPGA/GPP processors. This idea is reinforced by the 2015 Intel aqcusition of Alterra and AMD’s acquistion of Xilinx 2022. Both companies talk about how this combined approach can offer increased flexibility for developers. Here, the authors argue that due to the rapid advancements of GPPs, specialized processors have not had the chance to emerge.
Side-Channel Disassebmly
Proposed System
Ring Oscilators
System
Timing
Evaluation
Results
This work is ongonig, and is expected to be finished around Nov. 2023.
